Very large scale integrated circuits (VLSI) have seen increasing use of built-in test circuits that are utilized to either self-test the circuit or enhance board testing of the circuit. These circuits have emerged as a solution to the costs and complexity of testing these large circuit arrays, some of which can exceed 20,000 individual gates. As the densities increase, the need for more versatile test circuits also increases.
Testing of a VLSI array is done at a number of levels depending upon the complexity and the desired results. Lab testing is one stage of testing that requires both AC and DC parameter verification and a provision for debugging of the circuit. Lab testing usual requires that each input of the device be controlled for each test which can present a problem due the number of wires and probes and associated equipment required. In another type of testing, automatic testing, a large percentage of time is involved in DC parametric measurements which requires substantial "setting-up time." This is due to the internal logic which must be accounted for in determining the desired state on the outputs. It may take several sequences of input data and measurement cycles to test all the outputs in the automatic testing scheme.
Life testing is another type of testing which requires exercising the device in a controlled environment such as an oven. In addition to the limitations in the above testing, in lifetesting it is necessary to exercise the device under maximum power consumption to ensure that the device is properly stressed. Power consumption of large pin count devices is highly dependent on the state of the output. Depending upon the type of test circuit implemented in the device, it may be difficult if not impossible to place multiple bus devices in the worst-case power condition due to lack of total input control.
Another advantage sought through built-in test circuits is fault isolation at the board level. This is complicated by the number of devices that exist on a single bus. Typically, devices are either removed or traces cut until the fault is found. This technique can be tedious if the fault results only from a certain sequence of test inputs which must be repeated each time a change is made to see if the problem was isolated. This usually results in the entire test sequence being repeated until the fault is determined, which may take many iterations. A yet further advantage sought from built-in test circuit is one hundred percent AC and functional testing. This can be complicated when internal flip-flops are present in multiple paths since the prior state of the element must be considered in all test sequences and delay measurements.
Prior testing systems have solved some of the above problems by providing enable pins which place the outputs in a three-state mode. In addition, internal nodes on VLSI devices are functionally tested with such methods as LSSD, Signature analysis and built-in self-testing. However, none of these methods provide for the most time consuming test which is the DC parametric test nor do they provide for bench testing or life testing of the devices.